Wednesday Program

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UTC+2 Wednesday May 26, 2021
12:30 – 13:30
ETTTC meeting @ ETS
14:00 – 15:00 Session 9 – Miscellaneous
Chair(s): Mihalis Psarakis & Maria Mushtaq
14:00 – 14:20 S9-1 (CS) Exploiting Active Learning for Microcontroller Performance Prediction, Nicolò BELLARMINO, Riccardo CANTORO (Politecnico di Torino – Italy), Martin HUCH (Infineon Technologies AG – Germany), Tobias KILIAN (Infineon Technologies AG, Technical University of Munich – Germany), Raffaele MARTONE (Politecnico di Torino – Italy), Ulf SCHLICHTMANN (TUM – Germany), Giovanni SQUILLERO (Politecnico di Torino – Italy)
14:20 – 14:40 S9-2 (CS) An Ordinal Optimization-Based Approach To Die Distribution Estimation For Massive Multi-site Testing Validation: A Case Study, Isaac BRUCE, Praise FARAYOLA (Iowa State University – United States), Shravan CHAGANTI, Abalhassan SHEIKH, Abdullah OBAIDI (Texas Instruments – United States), Srivaths RAVI (Texas Instruments – India), Degang CHEN (Iowa State University – United States)
14:40 – 14:45 S9-3 (P) Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering, Katherine Shu-Min LI (National Sun Yat-sen University – Taiwan), Leon Li-Yang CHEN (NXP Semiconductors Taiwan Ltd. – Taiwan), Peter Yi-Yu LIAO, Ken Chau-Cheung CHENG (NXP Semiconductor Taiwan Ltd. – Taiwan), Sying-Jyan WANG (National Chung-Hsing University – Taiwan), Andrew Yi-Ann HUANG, Leon CHOU, Nova Cheng-Yen TSAI, Chen-Shiun LEE (NXP Semiconductor Taiwan Ltd. – Taiwan), Gus Chang-Hung HAN (National Chung-Hsing University – Taiwan), Jwu E CHEN (NCU – Taiwan), Hsing-Chung LIANG (Chung Yuan Christian University – Taiwan), Chun-Lung HSU (Industrial Technology Research Institute – Taiwan)
14:45 – 14:50 S9-4 (P) TDMS Test Scheduler: An Integrated Framework for Test Scheduling of DVFS-based SoCs with multiple voltage islands, Fotios VARTZIOTIS (University of Ioannina – Greece)
14:50 – 14:55 S9-5 (P) GPU-based ATPG System by Scaling Memory Usage and Reducing Data Transfer, Hua-Ren LI, Hsing-Chung LIANG (Chung Yuan Christian University – Taiwan)
Special Session 3 – Recent Advances on Photonic Physical Unclonable Functions
Organizer: Fabio PAVANELLO
14:00 – 14:20 SP3-1 Can Optical PUFs Save Us? A Subjective Perspective, Ulrich Rührmair (University of Connecticut – USA)
14:20 – 14:40 SP3-2 Physical Keys in Silicon Photonics, Amy Foster (John Hopkins University – USA)
14:40 – 15:00 SP3-3 Photonic Physical Unclonable Functions based on scattering random optical media: Optical Speckle response / key generation and its relation to the structured light input properties, Dimitris Syvridis (University of Athens – Greece)
Vendor Session 4: Innovative Test Approaches
Moderator(s): Erik Bury & Andrea Ganio
14:00 – 14:20 VS4-1 Precision Static ADC Test: Using Cost-Optimized Sinusoidal Methodologies on Advantest V93000, Matthias Werner (Advantest Europe – Germany)
14:20 – 14:40 VS4-2 ISOVU Technology – A Radically New Probing Solution, Sven De Coster (CN Rood – Belgium)
14:40 – 15:00 VS4-3 How To Keep Testing of New Generation Silicon Affordable in The Future, Armando FERNANDEZ (Salland Test Technology Center – the Netherlands)
15:00 – 16:00
Embedded Tutorials
ET-1 Speed-path Validation, Silicon Debug, Delay Test, Arani SINHA (Intel); Sandip RAY (U Florida)
Chair: Patrick Girard (LIRMM/CNRS – France)
ET-2 Security and Resilience of Quantum Computing, Swaroop GHOSH (Pennsylvania State University)
Chair: Samah Saeed (The City College of New York – USA)
ET-3 Analog Test Automation – An Overview of IEEE P1687.2, Hans Martin von STAUDT (Dialog Semiconductor), Steve SUNTER (Mentor a Siemens Business)
Chair: Haralampos Stratigopoulos (Sorbonne University – France)
16:00 – 16:30 Break & Vendor Booths
16:30 – 17:30
Keynote Address
A Cambrian Explosion in Electronic System Testing is Dead Ahead
Subhasish MITRA

Professor – Stanford University – Palo Alto, CA, USA
Moderator: Michele Stucchi
17:30 – 18:30 PhD Forum & Posters Session & MCCluskey Award
PF-1 ARCHITECTURAL-SPACE EXPLORATION OF ENERGY-EFFICIENT APPROXIMATE ARITHMETIC UNITS FOR ERROR-TOLERANT APPLICATIONS, Haroon WARIS, Chenghua WANG, Weiqiang LIU
PF-2 HOW SGX SECURITY CLAIMS MEET REAL LIFE SCENARIOS, Valentin MARTINOLI, Regis LEVEUGLE, Yannick TEGLIA
PF-3 BRIEF OVERVIEW ON LOGIC IN MEMORY SOLUTIONS, Pietro INGLESE, Elena Ioana VATAJELU, Giorgio DI NATALE
PF-4 NEURON FAULT TOLERANCE IN SPIKING NEURAL NETWORKS, Theofilos SPYROU, Sarah ALI EL-SAYED, Engin AFACAN, Luis Alejandro CAMUNAS MESA, bernabe LINARES-BARRANCO, Haralampos STRATIGOPOULOS
PF-5 TOWARDS RELIABILITY OF SNNS: DEFECT MODELING AND SIMULATION ON STT-MRAM CELL, Salah DADDINOUNOU, Elena Ioana VATAJELU
PF-6 NOVEL ATTACK AND DEFENSE STRATEGIES FOR ENHANCED LOGIC LOCKING SECURITY, Lilas ALRAHIS, Hani SALEH
P-1 A Tutorial of How to Ensure High Automotive Microcontroller Quality, Ralf ARNOLD (Infineon Technologies – Germany)
P-2 A 3DIC interconnect interface test and repair scheme based on Hybrid IEEE1838 Die Wrapper Register and BIST circuit, Changming CUI, Junlin HUANG (Hisilicon – China)
P-3 Opacity preserving Countermeasure using Finite State Machines against Differential Scan Attacks, Sk. Subidh ALI (IIT Bhilai – India), Yogendra SAO (Indian Institute of Technology Bhilai – India), Santosh BISWAS (IIT Bhilai – India)
P-4 Trustworthy computing on untrustworthy and Trojan-infected on-chip interconnects, Heba SALEM, Nigel TOPHAM (The University of Edinburgh – United Kingdom)
P-5 Transit-Guard: An OS-based Defense Mechanism Against Transient Execution Attacks, Maria MUSHTAQ, David NOVO (LIRMM – France), Florent BRUGUIER, Pascal BENOIT (Universite de Montpellier – France), Muhammad Khurram BHATTI (Information Technology University – Pakistan)
P-6 Chill Out: Freezing Attacks on Capacitors and DC/DC Converters, Obi NNOROM JR, Jalil MORRIS (Yale University – United States), Ilias GIECHASKIEL (Independent Researcher – United Kingdom), Jakub SZEFER (Yale University – United States)
P-7 Hierarchical Fault Simulation of Deep Neural Networks on Multi-Core Systems, Masoomeh KARAMI, Mohammad-Hashem HAGHBAYAN (University of Turku – Finland), Masoumeh EBRAHIMI (KTH – Sweden), Antonio MIELE (Politecnico di Milano – Italy), Hannu TENHUNEN (KTH – Sweden), Juha PLOSILA (University of Turku – Finland)
P-8 Analyzing the Impact of Approximate Adders on the Reliability of FPGA Accelerators, Ioannis TSOUNIS, Athanasios PAPADIMITRIOU, Mihalis PSARAKIS (University of Piraeus – Greece)
P-9 Online Testing of a Row-Stationary Convolution Accelerator, Mohammad Rasoul ROSHANSHAH, katayoon BASHARKHAH, Zainalabedin NAVABI (University of Tehran – Iran, Islamic Republic of)
P-10 Design of Fault-Tolerant and Thermally Stable XOR Gate in Quantum Dot Cellular Automata, Syed Farah NAZ, Ambika Prasad SHAH (Indian Institute of Technology Jammu), Suhaib AHMED (Baba Ghulam Shah Badshah University), Patrick GIRARD (LIRMM), Michael WALTL (Institute for Microelectronics, TU Wien)
P-11 Automatic Inspection for Wafer Defect Detection with Unsupervised Clustering Techniques, Katherine Shu-Min LI (National Sun Yat-sen University – Taiwan), Leon Li-Yang CHEN (NXP Semiconductors Taiwan Ltd. – Taiwan), Peter Yi-Yu LIAO, Ken Chau-Cheung CHENG (NXP Semiconductor Taiwan Ltd. – Taiwan), Sying-Jyan WANG (National Chung-Hsing University – Taiwan), Andrew Yi-Ann HUANG, Leon CHOU, Nova Cheng-Yen TSAI, Chen-Shiun LEE (NXP Semiconductor Taiwan Ltd. – Taiwan), Gus Chang-Hung HAN (National Chung-Hsing University – Taiwan), Jwu E CHEN (NCU – Taiwan), Hsing-Chung LIANG (Chung Yuan Christian University – Taiwan), Chun-Lung HSU (Industrial Technology Research Institute – Taiwan)
P-12 TDMS Test Scheduler: An Integrated Framework for Test Scheduling of DVFS-based SoCs with multiple voltage islands, Fotios VARTZIOTIS (University of Ioannina – Greece)
P-13 GPU-based ATPG System by Scaling Memory Usage and Reducing Data Transfer, Hua-Ren LI, Hsing-Chung LIANG (Chung Yuan Christian University – Taiwan)
MC-1 Leaky Hardware: Modeling and Exploiting Imperfections in Embedded Devices, Ilias GIECHASKIEL (University of Oxford)
MC-2 Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions, Lizhou WU (Delft University of Technology)
MC-3 Security Techniques for Test Infrastructures, Emanuele VALEA (LIRMM – CNRS)
MC-4 Efficient Post-Silicon Debug Framework for Future Many-Core Systems, Sidhartha Sankar ROUT (Indraprastha Institute of Information Technology)
MC-5 Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins, Jeremie KIM (Carnegie Mellon University)
MC-6 Assessing Dependability of ML-driven Systems, Saurabh Jha (University of Illinois at Urbana-Champaign)
MC-7 Effective techniques for systems validation and security, Aleksa Damljanovic (Politecnico di Torino)
18:30 – 19:30 Session 10 – Non-Volatile Memories
Chair(s): Rosa Rodriguez
18:30 – 18:50 S10-1 Intermittent Undefined State Fault in RRAMs, Moritz FIEBACK (Delft University of Technology – Netherlands), Guilherme CARDOSO MEDEIROS (TU Delft – Netherlands), Anteneh GEBREGIORGIS (Delft University of Technology – Netherlands), Hassen AZIZA (IM2NP – Aix-Marseille Université – France), Mottaqiallah TAOUIL, Said HAMDIOUI (Delft University of Technology – Netherlands)
18:50 – 19:10 S10-2 MBIST-supported Trim Adjustment to Compensate Thermal Behavior of MRAM, Christopher MÜNCH (Karlsruhe Institute of Technology – Germany), Jongsin YUN (Mentor – United States), Martin KEIM (Mentor, a Siemens Business – United States), Mehdi TAHOORI (Karlsruhe Institute of Technology – Germany)
19:10 – 19:30 S10-3 Convolutional Compaction-Based MRAM Fault Diagnosis, Jerzy TYSZER (Poznan University of Technology – Poland), Martin KEIM (Mentor, a Siemens Business – United States), Artur POGIEL (Mentor Graphics – Poland), Janusz RAJSKI (Mentor, A Siemens Business – United States), Bartosz GRZELAK (Poznan University of Technology – Poland)
Special Session 4 – Security, Reliability and Test Aspects of the RISC-V Ecosystem
Organizer: Francesco REGAZONI
18:30 – 18:45 SP4-1 How RISC-V can help in security research, Frank K. Gürkaynak (ETH Zurich – Switzerland)
18:45 – 19:00 SP4-2 Thwarting Differential Power Analysis Attacks on RISCV processors, Michael Hutter, Elke De Mulder, Helena Handschuh (Rambus – USA)
19:00 – 19:15 SP4-3 SW-only and HW/SW support for diverse redundancy for high-integrity applications, Jaume Abella (Barcelona Supercomputing Center – Spain)
19:15 – 19:30 SP4-4 Towards Bridging the Gap between System-level and Structural Test for the RISC-V Platform, Nourhan Elhamawy, Jens Anders, Steffen Becker, Matthias Sauer, Stefan Wagner, Ilia Polian (University of Stuttgart and Advantest – Germany)
Vendor Session 5: EDA
Moderator(s): Andreas Glowatz & Tom Waayers
18:30 – 18:50 VS5-1 Highly Accurate and Scalable Failure Diagnosis for Large Designs with Complex DfT Architectures, Sameer CHILLARIGE (Cadence Design Systems – India)
18:50 – 19:10 VS5-2 Siemens Presents Tessent Streaming Scan Network (SSN): No-Compromise DfT, Geir EIDE (Siemens EDA – United States)
19:10 – 19:30 VS5-3 Using Data Analytics to Debug and Trace Multi-Chip Module (MCM) Test Failures During the Manufacturing Process for Reducing Overall Test and Manufacturing Costs, Guy CORTEZ (Synopsys – United States)
Legend
Regular Session (S)
Special Session (SP)
Embedded Tutorial (ET)
Industry Session (IS)
McCluskey Award
PhD Forum & Poster Session
Keynote
Panel
Vendor Session
Regular Paper
(CS) Case Study Paper
(HT) Hot Topic Paper
(P) Poster
Best paper candidate