Wednesday Program

UTC+2 Wednesday May 26, 2021
14:00 – 15:00 Session 9 – Miscellaneous
14:00 – 14:20 (CS) Exploiting Active Learning for Microcontroller Performance Prediction, Nicolò BELLARMINO, Riccardo CANTORO (Politecnico di Torino – Italy), Martin HUCH (Infineon Technologies AG – Germany), Tobias KILIAN (Infineon Technologies AG, Technical University of Munich – Germany), Raffaele MARTONE (Politecnico di Torino – Italy), Ulf SCHLICHTMANN (TUM – Germany), Giovanni SQUILLERO (Politecnico di Torino – Italy)
14:20 – 14:40 (CS) An Ordinal Optimization-Based Approach To Die Distribution Estimation For Massive Multi-site Testing Validation: A Case Study, Isaac BRUCE, Praise FARAYOLA (Iowa State University – United States), Shravan CHAGANTI, Abalhassan SHEIKH, Abdullah OBAIDI (Texas Instruments – United States), Srivaths RAVI (Texas Instruments – India), Degang CHEN (Iowa State University – United States)
14:40 – 14:45 (P) Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering, Katherine Shu-Min LI (National Sun Yat-sen University – Taiwan), Leon Li-Yang CHEN (NXP Semiconductors Taiwan Ltd. – Taiwan), Peter Yi-Yu LIAO, Ken Chau-Cheung CHENG (NXP Semiconductor Taiwan Ltd. – Taiwan), Sying-Jyan WANG (National Chung-Hsing University – Taiwan), Andrew Yi-Ann HUANG, Leon CHOU, Nova Cheng-Yen TSAI, Chen-Shiun LEE (NXP Semiconductor Taiwan Ltd. – Taiwan), Gus Chang-Hung HAN (National Chung-Hsing University – Taiwan), Jwu E CHEN (NCU – Taiwan), Hsing-Chung LIANG (Chung Yuan Christian University – Taiwan), Chun-Lung HSU (Industrial Technology Research Institute – Taiwan)
14:45 – 14:50 (P) TDMS Test Scheduler: An Integrated Framework for Test Scheduling of DVFS-based SoCs with multiple voltage islands, Fotios VARTZIOTIS (University of Ioannina – Greece)
14:50 – 14:55 (P) GPU-based ATPG System by Scaling Memory Usage and Reducing Data Transfer, Hua-Ren LI, Hsing-Chung LIANG (Chung Yuan Christian University – Taiwan)
Special Session 3 – Recent Advances on Photonic Physical Unclonable Functions, Organizer: Fabio PAVANELLO
Vendor Session 4: Innovative Test Approaches
14:00 – 14:20 Precision Static ADC Test: Using Cost-Optimized Sinusoidal Methodologies on Advantest V93000, Matthias Werner (Advantest Europe – Germany)
14:20 – 14:40 ISOVU Technology – A Radically New Probing Solution, Sven De Coster (CN Rood – Belgium)
14:40 – 15:00 How To Keep Testing of New Generation Silicon Affordable in The Future, Paul VAN ULSEN, Armando FERNANDEZ, Gerwin VELTINK, Kim KOOL (Salland Test Technology Center – the Netherlands)
15:00 – 16:00 Embedded Tutorial 1 – Speed-path Validation, Silicon Debug, Delay Test,
Speakers: Arani SINHA (Intel); Sandip RAY (U Florida)
Abstract: This tutorial focuses on speed path validation, on challenges and state of the practice. Fundamental speed-path isolation techniques such as shmoo, clock skew, and laser-assisted device alteration, will be discussed, as well as newer CAD flows based on formal methods. Similarities, differences, and synergies between delay testing, static timing analysis, and speed-path validation will be covered, as well as opportunities for collaboration.
Embedded Tutorial 2 – Security and Resilience of Quantum Computing,
Speaker: Swaroop GHOSH (Pennsylvania State University)
Abstract: Qubits, which are building blocks of quantum computers, are fragile and prone to noise and error. Some prominent errors include decoherence/ dephasing, gate error, readout error, leakage, and crosstalk. The computation quality degrades in the presence of errors. This tutorial will provide an overview of various noise sources and their impact on the resilience and the security of quantum circuits. We will show that noise sources (e.g., crosstalk) create a new attack surface (e.g., fault injection and information leakage), especially for future large-scale quantum computers that may employ a multi-programming compute model. We will also cover countermeasures against the reliability and security issues.
Embedded Tutorial 3 – Analog Test Automation – An Overview of IEEE P1687.2,
Organisers: Hans Martin von STAUDT (Dialog Semiconductor), Steve SUNTER (Mentor a Siemens Business)
Abstract: In this tutorial we will introduce the major elements of 1687.2 deep enough such that they can be applied to practical examples. After showing how the gaps in the status quo of A/MS testing shall be addressed the tutorial will start with the new analog language elements of ICL and PDL. From that we will create basic analog DFT building blocks, which are then applied to create the mixed-signal DfT infrastructure of a chip. The tutorial will show how test procedures, developed on IP level, can be retargetted either to on-chip instruments or to the chip top-level, where they are mapped to commercial ATE instruments.
16:00 – 16:30 Break & Vendor Booths
16:30 – 17:30
Keynote Address
A Cambrian Explosion in Electronic System Testing is Dead Ahead
Subhasish MITRA

Professor – Stanford University – Palo Alto, CA, USA
17:30 – 18:30 Panel
18:30 – 19:30 Session 10 – Non-Volatile Memories
18:30 – 18:50 Intermittent Undefined State Fault in RRAMs, Moritz FIEBACK (Delft University of Technology – Netherlands), Guilherme CARDOSO MEDEIROS (TU Delft – Netherlands), Anteneh GEBREGIORGIS (Delft University of Technology – Netherlands), Hassen AZIZA (IM2NP – Aix-Marseille Université – France), Mottaqiallah TAOUIL, Said HAMDIOUI (Delft University of Technology – Netherlands)
18:50 – 19:10 MBIST-supported Trim Adjustment to Compensate Thermal Behavior of MRAM, Christopher MÜNCH (Karlsruhe Institute of Technology – Germany), Jongsin YUN (Mentor – United States), Martin KEIM (Mentor, a Siemens Business – United States), Mehdi TAHOORI (Karlsruhe Institute of Technology – Germany)
19:10 – 19:30 Convolutional Compaction-Based MRAM Fault Diagnosis, Jerzy TYSZER (Poznan University of Technology – Poland), Martin KEIM (Mentor, a Siemens Business – United States), Artur POGIEL (Mentor Graphics – Poland), Janusz RAJSKI (Mentor, A Siemens Business – United States), Bartosz GRZELAK (Poznan University of Technology – Poland)
Special Session 4 – Security, Reliability and Test Aspects of the RISC-V Ecosystem, Organizer: Francesco REGAZONI
Vendor Session 5: EDA
18:30 – 18:50 Highly Accurate and Scalable Failure Diagnosis for Large Designs with Complex DfT Architectures, Sameer CHILLARIGE (Cadence Design Systems – India)
18:50 – 19:10 Siemens Presents Tessent Streaming Scan Network (SSN): No-Compromise DfT, Geir EIDE (Siemens EDA – United States)
19:10 – 19:30 Using Data Analytics to Debug and Trace Multi-Chip Module (MCM) Test Failures During the Manufacturing Process for Reducing Overall Test and Manufacturing Costs, Guy CORTEZ (Synopsys – United States)
Legend
Regular Session (S)
Special Session (SS)
Embedded Tutorials (ET)
Industrial Session (IS)
McCluskey Award
PhD Forum & Posters
Keynote
Panel
Vendor Session
Regular Paper
(CS) Case Study Paper
(HT) Hot Topic Paper
(P) Poster