Vendor Sessions

ETS2021 has in total five Vendor Sessions, each consisting of three presentations by commercial vendors. Vendor Session presentations differ from other ETS presentations in that company names, logos, and product names may be mentioned explicitly. Typical content of these Vendor Session presentations includes technical product descriptions, case studies, best practices, and user testimonials of products or solutions. Although these Vendor Session presentations are obviously not reviewed or otherwise screened by the ETS program committee, the ETS organizers instruct the presenters to target ETS’ technical audience, who typically favor real technical content over marketing-only presentations.

Vendor Session 1: Test Equipment

Monday, May 24th, 2021, 18:00 – 19:00 UTC+2

Session Moderator(s): Bram KRUSEMAN (NXP Semiconductors – the Netherlands), Hans MANHAEVE (imec – Belgium)

18:00 – 18:20 Solving Test Challenges of State-of-the-Art Power Devices
Thomas KOEHLER*, Dennis KEOGH, Chuck CARLINE (Teradyne – USA)

The global power electronics market is anticipated to exhibit a healthy growth rate over the next several years and has taken an even more important role in the future to improve energy conservation in a variety of applications such as consumer electronics, automotive, electric automobiles, and industrial systems. This presentation describes current and future power semiconductors trends and how the floating architecture of the Eagle platform is optimally suited to test state of the art power semiconductors.

18:20 – 18:40 Keysight’s Massively Parallel Board Test System
Sivakumar VIJAYAKUMAR* (Keysight Technologies – Singapore)

Learn about Keysight’s new solution that enables testing of high-volume products using a massively parallel board test system.

18:40 – 19:00 Improving Reliability Insights Through Cost-Effective, Flexible Parallel WLR Systems
Joris DONDERS* (NI – Belgium)

With innovation in node and process technology there is an increasing need for more reliability insights. These insights require large amounts of data which can be very time consuming or forces tradeoffs to be made. During this session attendees will learn about new capabilities on the market to build high throughput, high channel count parallel reliability setups enabled through an open software approach providing maximum flexibility.


Vendor Session 2: OpenTAP Tutorial

Tuesday May 25th 2021, 16:30 – 17:30 UTC+2

Session Moderator(s): Erik LARSSON (Lund University – Sweden), Jouke VERBREE (NXP Semiconductors – the Netherlands)

16:30 – 16:50 Going Open (Source), the Future of Test & Measurement Automation
Jeff DRALLA* (Keysight Technologies – USA), Michael DIEUDONNE (Keysight Technologies – Belgium)

The story of how Keysight Technologies (formerly Agilent Technologies and the original T&M arm of Hewlett-Packard), with a long history of proprietary commercial products and measurement science IP, decided to open source a software project for the first time in their 80+ year history. Hear about what caused this change in mindset, the challenges along the way, the benefits it brought to those involved, and how it plans to revolutionize the rest of the T&M industry.

16:50 – 17:10 OpenTAP: The Open Source Path To Effortless Automation
Brennen DIRENZO* (Keysight Technologies – USA)

No one ever gets fired for using the same legacy approach year after year, right? Triggered by product launch delays from homegrown testing software and concerns from the management team about vendor lock-in, a change angel revolutionizes their projects (TM) test automation approach, transforms their organization, and, ultimately, advances their own career (and their colleagues too)!

17:10 – 17:30 OpenTAP Enables Massively Parallel Board Tester on Keysight System
Sivakumar VIJAYAKUMAR* (Keysight Technologies – Singapore)

Learn how OpenTAP unleashes the power of automation and customization of test strategy and solution using a massively parallel board test system as a case study.


Vendor Session 3: Wafer Probe Technology

Tuesday May 25th, 2021, 18:0-19:0 UTC+2

Session Moderator(s): Jeroen DE COSTER (imec – Belgium), Stojan Kanev (MPI Corporation – Germany)

18:00 – 18:20 Improving Parametric Test Quality and Efficiency with XP5 Probe Material
Joe Mai* (JEM Europe – France), Romain LAVEVILLE, Guillaume DUTERTRE* (ST Microelectronics – France)

Parametric tests of semiconductor devices face a multitude of challenging trends: shrinking device dimensions, new pad materials, fragile pad structures, higher (or lower) voltages, higher currents (with lower Rdson), lower noise margins, high/low temperatures, etc. Often these challenges are competing and require compromises in the probing solution. For example, smaller pads require smaller probe tips, whereas higher currents tend to require larger tips. A critical consideration for addressing all of these challenges is the probe material. Low and stable contact resistance (CRES) and minimal pad damage are key requirements. In this presentation, the authors will present a unique probe material, XP5, which has been shown to address many of the above challenges, while reducing the overall cost of test.
The presentation will be in two parts, a vendor section presenting an overview of recent probing challenges, with examples of how XP5 has helped to address them, followed by a customer section presenting an evaluation of XP5 in a production environment.
Although traditional tungsten-rhenium (WRe) probes had proved durable and efficient for parametric test, they require high pressure and long scrub marks to maintain good CRES, which requires large and mechanically robust pads. However, as device technologies evolve and cost competition increases, smaller pads are needed. The XP5 mechanical and electrical characteristics helped solve this challenge, providing reductions in pressure, scrub-mark size, and CRES, which allows smaller and more fragile pads while improving measurement repeatability. Finally, these technical benefits also lower overall test costs by improving tester utilization and reducing operator interventions due to probe-card-related issues.

18:20 – 18:40 Flexible Wafer-Level Optical Probing Solutions: Meeting the Cycle-Time Demands of Engineering to High-Volume Silicon Photonics Manufacturing
Dan Rishavy* (FormFactor – USA)

The integration of optical components on a chip creates a host of new challenges and demands for wafer-level probing of photonics devices, where huge volumes of device-performance data are required to carry a design from concept to qualification and into production. While working in a lab on an initial prototype, it may suffice to spend minutes or in some cases hours to setup and align a single device for measurements. However, such time- and effort-intensive methods are unsuitable for the cycle-time demands of high-volume silicon photonics manufacturing. Due to the industry demand for a wide range of applications, a flexible probing platform is needed that can be quickly optimized for the needs of the application. Numerous parameters can be configured on FormFactor’s wafer probers to enable optical, RF, DC, wafer level, die level, surface coupling, edge coupling, and probe cards. While maintaining the required alignment performance requirements in terms of accuracy, throughput, and power coupling repeatability. Come to this session to learn more about FormFactor’s exciting technology enabling the silicon photonics market expansion.

18:40 – 19:00 Fine-Pitch WLCSP Spring Probe Pointing Accuracy and Wobble
Bert Brost* (Technoprobe America – United States)

As Wafer-Level Chip-Scale Packaging (WLCSP) pitch shrinks to ≤ 200 microns and I/O counts increase, WLCSP spring probe pointing accuracy or ‘wobble’ is a topic of increasing interest. The test point accuracy which can be achieved is determined by the tolerances and mating spring probe component ratios. The dependence on the plunger length in relation to the effective plunger guide length and probe body and plunger load bearing surfaces are critical factors. These factors that must be understood for effective use of fine-pitch WLCSP spring probe. New probe designs and manufacturing processes are effectively addressing the issues of lateral play at the plunger tip. In addition to the factors mentioned, a new spring probe geometry is required for reliable and repeatable prober optical alignment to the WLCSP spring probe tip, i.e., a deterministic location of the spring probe in the probe head body is required.


Vendor Session 4: Innovative Test Approaches

Wednesday May 26th, 2021, 14:00 – 15:00 UTC+2

Session Moderator(s): Erik BURY (imec – Belgium), Andrea Ganio (SPEA – Italy)

14:00 – 14:20 Precision Static ADC Test: Using Cost-Optimized Sinusoidal Methodologies on Advantest V93000
Matthias Werner* (Advantest Europe – Germany)

Today, most ADCs inside consumer and automotive devices are tested using a static ramp methodology. New generation of devices require a more precise and linear analog test signal in the few hundred of uV range. Applying more precise analog test instrumentation is expensive, therefore cannot meet the cost of test targets. Most papers presented on sinusoidal ADC testing focus on the dynamic performance of very high resolution and high-performance devices. Consumer and automotive ADCs, however, are typically in the 12bit range and statically specified using parameters such as TUE, DNL, INL, offset and gain. Furthermore, sinusoidal dynamic testing increases test time proportionally, which is a contradiction to a cost optimized test strategy. Therefore, a new concept had to be developed to meet the target test cost, parallelism, and test time, as well as test parameters that meet ADC specification targets. This paper describes this new methodology, deployment, and result performance. A pulse width modulated sinusoidal test signal is used for precision static ADC testing without compromising test time. It will illustrate the generation of high-performance stimulus signals, and the deployment and methodology of newly invented signal processing techniques to achieve fast and precise measurement results for static ADC test parameters. To meet the cost of test target, only available digital channels are used for this measurement technique. Furthermore, correlation to precision reference instrumentation as well as traditional static ADC ramp test methodology will also be demonstrated.

14:20 – 14:40 ISOVU Technology – A Radically New Probing Solution
Sven De Coster* (CN Rood – Belgium)

In this presentation we introduce the Tektronix IsoVu technology as a radically new high voltage isolated differential probing solution. This technology helps electronic design engineers with their – typically – GaN or SiC base developments.

14:40 – 15:00 How to Keep Testing of New Generation Silicon Affordable in the Future
Armando FERNANDEZ* (Salland Test Technology Center – the Netherlands)

This paper will highlight a new “way of working” to develop state of the art test IP to test new generation silicon by using of flexible business models. Nowadays silicon is getting more complex, time to market needs to be faster, lifetime is getting shorter and of course we have to deal with the never-ending story about Cost of Test (COT). All these aspects are also related to higher demand and requirements for test instruments used for characterization and production testing of modern silicon. At Salland we develop innovative test technology IP for MEMS Sensors, Flexible IO and Engineering tools to make life of a designer/engineer easier and make testing possible. During this session we will present our specific developed technology to test MEMS, and other sensors, without physical stimulus. Another aspect we will present is the possibility of using Test-IP-Building blocks to address the COT topic and bring the design environment close to volume testing.


Vendor Session 5: Electronic Design Automation and DfT

Wednesday May 26th, 2021, 18:30 – 19:30 UTC+2

Session Moderator(s): Andreas GLOWATZ (Siemens EDA – Germany), Tom WAAYERS (NXP Semiconductors – the Netherlands)

18:30 – 18:50 Highly Accurate and Scalable Failure Diagnosis for Large Designs with Complex DfT Architectures
Sameer CHILLARIGE* (Cadence Design Systems – India)

Accuracy, resolution and performance of a scan-based failure diagnosis tool is extremely critical for enabling faster silicon bring-up and yield ramp. The diagnosis challenges get exacerbated by ever increasing design sizes, complex DfT architectures and new defect types making the overall process much more tedious and resource intensive. This presentation covers high level diagnostics capabilities of Modus DfT Software Solution and then deep-dives in to some of the diagnostics challenges and how Modus Diagnostics addresses these and enables high accuracy, resolution and performance.

18:50 – 19:10 Siemens Presents Tessent Streaming Scan Network (SSN): No-Compromise DfT
Geir EIDE* (Siemens EDA – USA)

The increasing complexity in large System on Chip (SoC) designs present challenges to design-for-test (DfT). Hierarchical DfT is no longer enough. Tessent Streaming Scan Network (SSN) technology eliminates the difficult and costly trade-offs between test implementation effort and manufacturing test cost by decoupling core-level and chip-level DfT. With SSN, a true no-compromise approach to DfT is possible.

19:10 – 19:30 Using Data Analytics to Debug and Trace Multi-Chip Module (MCM) Test Failures During the Manufacturing Process for Reducing Overall Test and Manufacturing Costs
Guy CORTEZ* (Synopsys – USA)

Seeing your MCM packaged chips fail late in the manufacturing process during Final Test is never a welcoming sight especially due to the lost opportunity of selling these chips but also due to the inability to recoup the high costs associated with the testing and packaging that went into the manufacturing of these failed MCM packaged chips. Using data analytics throughout the various manufacturing test stages can possibly help find the source of the problem earlier in the manufacturing cycle. This paper introduces specific analytical methods such as data feed backward and data feed forward that enables test engineers to perform fast root cause analysis and find the source of where the issue originated. Test engineers can then further incorporate preventative measures to bin out suspected die earlier in the process preventing costly failures downstream. Come listen to a real-world customer example of how one customer used these methods together with a cloud-based data analytics solution to reduce their overall test and manufacturing costs.