Industry Sessions

The three ETS Industry Sessions give the floor to technical experts and their managers working in the semiconductor industry. Each presentation will be approximately 9 minutes, immediately followed by up to 9 minutes of discussion facilitated by two Chairs. This format offers longer scheduled presentation times than in a panel but shorter than for regular papers, and provides more opportunity for audience questions than for a regular paper.

Industry Session 1: Diagnosing Failing Mixed-Signal ICs

Automated diagnosis of defects in scan path tested digital circuitry is widely used in industry and has drastically reduced the time to address yield limiters. Analog defect diagnosis has been described in many research papers, but none has proposed techniques that could become comparable to those for digital circuits. How is industry diagnosing defects in mixed-signal ICs?

Organizers: Wim DOBBELAERE, Stephen SUNTER

Monday, May 24th, 2021, 15:30 – 16:30 UTC+2

Chairs: Haralampos STRATIGOPOULOS (Sorbonne University – France), Stephen SUNTER (Siemens EDA – Canada)

15:30 – 15:50 Diagnosis of SAR-ADC INL/DNL Failures using Capacitor Matching Techniques
Stefano ROGGI, Peter BOGNER, Rocco CALABRO, Josef NIEDERL, Dario VAGNI, Andreas FUGGER (Infineon Technologies – Austria), Jaafar MEJRI, Ralf ARNOLD (Infineon Technologies – Germany)
Accurate measurements of INL/DNL normally require a significant amount of test time during production test. This is caused by the stimuli that need to be applied with a substantial number of hits/code to the ADC. In addition, the classical technique cannot always be used for wafer test during which the ADC inputs are not connected to the ATE. BITE is an innovative digital-based analog BIST solution, requiring neither analog stimuli nor sensitive measurements, which makes it possible to evaluate key performance parameters like INL and DNL. The independence of the BITE from the ATE allows it to be used in virtually any test scenario. This opens up opportunities to perform the BITE during wafer test, burn-in, back-end test and even in mission mode for In-System Test.
15:50 – 16:10 Defect Oriented Diagnostic For Analog: Why Building a Defect Oriented Test Database Matters
Jo GUNNES (NXP Semiconductors – Netherlands)
16:10 – 16:30 Automated Analog Fault Simulators: Application to Failure Analysis
Tommaso MELIS (ST Microelectronics – France)
The increasing complexity of analog and mixed-signal circuit applications presents new challenges for manufacturing test and failure analysis. Nowadays, failure analysis on such circuits is particularly difficult to perform. The problem is even more pronounced in some critical application fields such as automotive. This is a functional safety field requiring fast and reliable failure analysis. To meet these requirements we have created an innovative diagnosis flow. It integrates the analog fault simulators with the standard failure analysis techniques. This robust diagnosis method has been applied to real analysis with successful results.

Industry Session 2: Solutions for Preventing Latent Defects from Causing System Faults

As test coverage improves through better DFT and test methods, a limitation to delivered quality is latent defects: defects that become evident only after a device passes test. Burn-in and HVST are widely used, and design and simulation techniques have been proposed to improve these. What is working in industry, and where is more progress needed?

Organizers: Wim DOBBELAERE, Stephen SUNTER

Monday, May 24th, 2021, 17:00 – 18:00 UTC+2

Chairs: Riccardo CANTORO (Politecnico di Torino – Italy), Mark ZWOLINSKI (University of Southampton, United Kingdom)

17:00 – 17:20 From Screening Latent Defects Towards Auto Correction
Ronny VANHOOREN, Anthony COYETTE, Wim DOBBELAERE (ON Semiconductor – Belgium) Jhon GOMEZ, Nektar XAMA, Georges GIELEN (KU Leuven – Belgium)
Many latent defects are identified as deformations in dielectric isolation. VSTRESS is an effective method to activate these, allowing them to be detected with costly burn-in. DFT can improve the effectiveness of this method. Such methods are cost effective but might not remove the last 100 ppb of early life failures. There is a need for a new design approach where auto-correction becomes active in the field, as used in EEPROM ECC, for example. This could be applied to large multi-finger DMOS transistors, where DFT could detect which finger is leaking and disable it.
17:20 – 17:40 Automotive Quality Requirements and Industrial Volume Production: Zero Defect Meets the Real World
Ralf MONTINO, Christian THUM (Elmos Semiconductor – Germany)
17:40 – 18:00 Techniques to Mitigate Latent Defects in the Digital World
Jeff REARICK (Advanced Micro Devices – United States)
Latent defects in digital circuits have been a concern for decades, and many techniques have evolved to deal with them, ranging from special production test steps to chip and system architectural features.

Industry Session 3: Analog Defect Simulation in Industry

Analog defect simulation has been described in published papers for about 30 years, but commercial simulators have been introduced in only the last 5 years. How well are simulators working for industry so far? Where are they more useful and less useful? What problems occur during defect simulation and how can they be solved?

Organizers: Wim DOBBELAERE, Stephen SUNTER

Tuesday, May 25th, 2021, 15:00 – 16:00 UTC+2

Chairs: Hans Martin VON STAUDT (Dialog Semiconductor – Germany), Martin ANDRAUD (Aalto University – Finland)

15:00 – 15:20 Analog Defect Coverage – History, Status Now and Challenges Still Ahead of Us
Dieter HAERLE, Jaafar MEJRI, Thierry VERNET (Infineon Technologies – Germany)
The topic “Analog Defect Coverage” has been around for quite some time, but only recently the topic got a kick-start due to the increasing compute resources available and also due to an industry-wide effort to standardize (IEEE P2427) analog defect modeling and coverage. This presentation will give a brief overview of the beginnings in the 90s, present some experiences and simulation results with currently available methodologies, and finally it will give an outlook about challenges and developments still ahead of us to be able to use this methodology in an industrial product development flow.
15:20 – 15:40 Analog Defect Simulators – Initial Successes and Remaining Challenges
Anthony COYETTE, Wim DOBBELAERE, Ronny VANHOOREN (ON Semiconductor – Belgium) Jhon GOMEZ, Nektar XAMA, Georges GIELEN (KU Leuven – Belgium)
In the last decade, the advent of Analog Defect Simulators has made it possible to take defect-oriented decisions based on simulated defect coverages. Moving forward, this enabling trend should support further the Design-for-Test community; three aspects will be covered in this talk. Firstly, the output of Analog Defect Simulators will be discussed looking at the use cases of Test Time Reduction and Defect Coverage Improvement. Secondly, the generation of simulation testbenches will be covered; this manual and cumbersome practice today should become semi-automated, possibly with the support of IEEE 1687.2. Finally, the talk will look into the reporting of metrics towards internal and external customers in perspective with the future IEEE 2427.
15:40 – 16:00 An Effective Iterative Method to Improve Mixed-Signal Manufacturing Test Quality
Fred FU, Yifan GE (HiSilicon – China)
Based on transistor-level defect modeling and a commercial defect simulator, this talk proposes an iterative evaluation method for mixed-signal circuit test coverage. The method, which prunes out uninteresting defects “dummy, redundancy, yield friendly” automatically or manually, has been used successfully in quantifying and improving the test coverage of some mixed-signal circuits, including LDO, ADC, SerDes, and POR cases, all of which can acquire the expected 95% test coverage with this flow.