Embedded Tutorials

Embedded Tutorial 1: Speed-path Validation, Silicon Debug, Delay Test

Speakers: Arani SINHA (Intel); Sandip RAY (U Florida)

Wednesday, May 26th, 2021, 15:00 – 16:00 UTC+2

Abstract: This tutorial focuses on speed path validation, on challenges and state of the practice. Fundamental speed-path isolation techniques such as shmoo, clock skew, and laser-assisted device alteration, will be discussed, as well as newer CAD flows based on formal methods. Similarities, differences, and synergies between delay testing, static timing analysis, and speed-path validation will be covered, as well as opportunities for collaboration.

Embedded Tutorial 2: Security and Resilience of Quantum Computing

Speakers: Swaroop GHOSH (Pennsylvania State University)

Wednesday, May 26th, 2021, 15:00 – 16:00 UTC+2

Abstract: Qubits, which are building blocks of quantum computers, are fragile and prone to noise and error. Some prominent errors include decoherence/ dephasing, gate error, readout error, leakage, and crosstalk. The computation quality degrades in the presence of errors. This tutorial will provide an overview of various noise sources and their impact on the resilience and the security of quantum circuits. We will show that noise sources (e.g., crosstalk) create a new attack surface (e.g., fault injection and information leakage), especially for future large-scale quantum computers that may employ a multi-programming compute model. We will also cover countermeasures against the reliability and security issues.

Embedded Tutorial 3: Analog Test Automation – An Overview of IEEE P1687.2

Speakers: Hans Martin von STAUDT (Dialog Semiconductor), Steve SUNTER (Mentor a Siemens Business

Wednesday, May 26th, 2021, 15:00 – 16:00 UTC+2

Abstract: In this tutorial we will introduce the major elements of 1687.2 deep enough such that they can be applied to practical examples. After showing how the gaps in the status quo of A/MS testing shall be addressed the tutorial will start with the new analog language elements of ICL and PDL. From that we will create basic analog DFT building blocks, which are then applied to create the mixed-signal DfT infrastructure of a chip. The tutorial will show how test procedures, developed on IP level, can be retargetted either to on-chip instruments or to the chip top-level, where they are mapped to commercial ATE instruments.